1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the management of aliasing within virtually indexed and physically tagged (VIPT) cache memories.
2. Description of the Prior Art
It is known within data processing systems to provide cache memories for increasing processor performance. These cache memories have tended to grow larger in size accompanying the general increase in data processing system performance. It is desirable within cache memories that the physical layout of the memory should have a certain aspect ratio to provide a good balance between speed, power consumption, area and other factors. Thus, for a given number of cache ways within a cache memory the size of those cache ways has tended to increase.
Also present within many data processing systems are mechanisms which support translation between virtual addresses and physical addresses. An example of such mechanisms is a memory management unit MMU which serves to translate virtual addresses to physical addresses on a page-by-page basis using page table entries. The page table entry specifies for a given contiguous block of virtual memory addresses what will be the corresponding contiguous block of physical memory addresses. A lookup in the MMU is typically performed in parallel with a lookup in the cache memory for performance reasons. Accordingly, it is known to use virtually indexed and physically tagged cache memories. As will be appreciated by those skilled in the art, in such cache memories the actual cache lookup is performed using a portion of the virtual address referred to as a virtual index. Herein, for simplicity, the term virtual address will be used throughout.
Within such systems where page table entries specify the mapping between virtual and physical addresses, the page size can vary. It is advantageous to have a variable page size to allow the mapping to be configured to match the requirements of the particular system or applications concerned.
A problem arises in virtually indexed and physically tagged memories when the size of a cache way exceeds the minimum page size. In these circumstances, it is possible for more than one virtual address within a cache way to map to the same physical address using respective page table entries (i.e. aliasing). One known way of dealing with this is to constrain the operating system to prevent it from allocating page table entries with page table sizes that can give rise to such aliasing issues. Another way of managing this is to constrain how the operating system allocates physical memory to ensure that all aliases for different virtual addresses which map to the same physical address all map to the same virtual index.